[ale] Dual core CPUs in cluster?

[Dow Hurst]

We decided against the dual core as the chips are expensive and won't be 
available til after our money has to be spent.  I think Intel is running 
into a wall with the frontside bus and huge onboard caches.  Our final 
config is going to be:

20 dual 250 Opteron nodes
Ammasso NICs
SMC TigerSwitch 8624T 24 port nonblocking wirespeed
80Gb root disks each node
2Gb PC3200 ECC RAM per node
Master node will have a 3Ware 8channel controller and 5 additional 250Gb 
SATA disks
APC Netshelter VX rack
3 SU3000RMT APC UPSes 208V input/output
Assorted cabling and PDUs

Local disks on slaves are for a particular application that needs a 
large local swap/scratch disk.  Otherwise I'd have gone diskless.  The 
company that won the bid is TeamHPC.  I've checked references and seven 
of the nine replied.  All were very favorable with great comments on 
quality of the hardware and support.  Large and small installations were 
part of the client list.  I was impressed with the comments and am 
excited about the situation.  My only real worry now is that I've picked 
the right switch for the cluster.  It is used by the developers of the 
main application we will run on the cluster, NAMD.  However, I haven't 
found a direct benchmark of the switch, just comments that it is a good 
compromise between exorbitantly priced low-latency Gig-E switches and 
lower cost switches that don't have the needed specs.  Even the Beowulf 
list doesn't have direct measurements of latency.  No one is complaining 
about it that I've found.  There isn't a rash of documentation saying 
"don't buy this switch"!
Dow


Jeffrey B. Layton wrote:

> James P. Kinney III wrote:
>
>> However, the datasheets I have looked at show something I don't like,
>> shared L1 and L2 cache. I don't recall if this is entirely accurate or
>> not or if it was a "special" version. It seems to me that a shared L1 is
>> asking for trouble. Shared L2 (the deepest data cache) would also be a
>> problem as both core would not be working on the same data thus
>> requiring a page out.
>>  
>>
>
>   For the AMD dual-core the L1 and L2 caches are all separate.
> There is a cross-bar in the chip though to help with memory
> access requests, etc.
>   The Intel dual-cores are the same but don't have a crossbar
> to help things. I've also read some rumors that in the next
> generation, Intel will be adding a L3 cache and may have a
> combined L2 cache across cores. If you can code for that
> kind of architecture then codes that need to communicate
> from core to core can just used the L2 to pass data. Theoretically
> a good idea, but probably difficult to code for.
>
>
> Jeff
>
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